Charleston Lake
Astronomical
Imaging the Night Sky from Ontario Canada
CCD Overview
How a CCD works (CCD = Charge Coupled Device)
A CCD camera's purpose is to
a) Convert photons into electrons, store the charge per pixel
b) Convert the electrons into digital data, which represents the photons (light)
c) Re-assemble the digital data in an array to form an image
The CCD Imaging Device provides the "conversion of photons into electrons" and the storing of the charge. The CCD chip is an array of pixels, each pixel is an individual cell that transfer charged electrons, representing the photons that strike the substrate. Together, the array of pixels, forms an image. Each pixel is like a small bucket of electron charge.
A CCD camera's purpose is to
a) Convert photons into electrons, store the charge per pixel
b) Convert the electrons into digital data, which represents the photons (light)
c) Re-assemble the digital data in an array to form an image
The CCD Imaging Device provides the "conversion of photons into electrons" and the storing of the charge. The CCD chip is an array of pixels, each pixel is an individual cell that transfer charged electrons, representing the photons that strike the substrate. Together, the array of pixels, forms an image. Each pixel is like a small bucket of electron charge.
CCD Pixel - Electron Charge
During Integration, the photons striking the CCD cause stored charge (electrons) to accumulate in each pixel (well). The integration time is set by the user.
Similiar to water, the stored electrons remain in the well. If the well becomes full, that pixel is "Saturated" and "blooming" occurs, where electrons spill into adjacent pixels, unless the CCD has an anti-blooming gate (ABG) which is an overflow drain. The CCD chip will have specified "full well" electrons per pixel, note that this is a different measurement than the camera ADU per pixel. A 16bit CCD camera will have 2^16 units (ADU) per pixel, 65,536 ADU.
The Pixels are arranged in Rows and Columns, per the animation below.
Similiar to water, the stored electrons remain in the well. If the well becomes full, that pixel is "Saturated" and "blooming" occurs, where electrons spill into adjacent pixels, unless the CCD has an anti-blooming gate (ABG) which is an overflow drain. The CCD chip will have specified "full well" electrons per pixel, note that this is a different measurement than the camera ADU per pixel. A 16bit CCD camera will have 2^16 units (ADU) per pixel, 65,536 ADU.
The Pixels are arranged in Rows and Columns, per the animation below.
Animation showing CCD integration, then data
being clocked out of the CCD with Shift Registers
being clocked out of the CCD with Shift Registers
When the integration is complete, the CCD wells will contain electrons representing the photons. Next, the integrated data is "clocked" out of the CCD chip. This is done using gates, where each pixel passes it's accumulated charge to an adjacent pixel.
The pixel array is made up of columns and rows. Shift Registers trigger the data out.
First, the column data is shifted parallel, (parallel, all of the columns together), down by 1 pixel, onto the serial bus.
Then, the serial bus indexes the data (serially, in a row) to the left one pixel at
a time. The serial data stream exists the output pin, synchronized to the clock.
Once the entire row has been serially clocked out of the chip, the parallel data can shift down by another pixel, then serially shift this row of data out of the CCD chip, repeating until the array is completed
This Parallel and Serial data clocking is typically controlled by an FPGA chip, sending pulse streams to the CCD Vertical and Horizontal pins.
The pixel array is made up of columns and rows. Shift Registers trigger the data out.
First, the column data is shifted parallel, (parallel, all of the columns together), down by 1 pixel, onto the serial bus.
Then, the serial bus indexes the data (serially, in a row) to the left one pixel at
a time. The serial data stream exists the output pin, synchronized to the clock.
Once the entire row has been serially clocked out of the chip, the parallel data can shift down by another pixel, then serially shift this row of data out of the CCD chip, repeating until the array is completed
This Parallel and Serial data clocking is typically controlled by an FPGA chip, sending pulse streams to the CCD Vertical and Horizontal pins.
The resultant data is an analog value per pixel which represents the photons captured by that pixel. This data is clocked in synchronization with the CCD Serial and Parallel data clocks, into an Analog to Digital converter, and the digital value per pixel is clocked onto the Data Bus, and into memory. The resolution of the A/D converter is typically 16 bit, the output data is ADU per pixel. For a 16 bit A/D converter, this would be 2 to the power of 16, which is 65,536 ADU counts max, for a fully saturated pixel. The data values are then assembled in an array, FITS format, for the final resultant image.
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